Field of the Invention
The invention relates to an epitaxial wafer and a method of manufacturing the same, and particularly, to technology suitable for an epitaxial wafer used in a process of forming a strained layer to improve a device characteristic.
Priority is claimed on Japanese Patent Application No. 2008-318897, filed Dec. 15, 2008, the content of which is incorporated herein by reference.
Description of the Related Art
As silicon devices become more and more miniaturized, the vicinity of the wafer surface which is the active layer of the device is often strained to improve device characteristics.
For example, a strained silicon wafer obtained by epitaxially growing a SiGe layer on a single-crystalline silicon wafer and epitaxially growing a strained silicon layer on the SiGe layer, a wafer obtained by changing the wafer from a SiGe layer to a nitriding of the surface, or a silicon-on-insulator (SOI) wafer have been proposed in the art.
In the strained silicon layer, a tensile strain is generated by the SiGe layer having a larger lattice constant than that of silicon. This tensile strain changes and degenerates a band structure of silicon so as to increase carrier mobility. By using the strained silicon layer as a channel region, the carrier mobility can increase 1.5 times or more in comparison with a semiconductor substrate using typical bulk silicon. Therefore, the strained silicon wafer is advantageously adaptable to a high-speed MOSFET (metal oxide semiconductor field effect transistor), a MODFET (modulation-doped field effect transistor), and a HEMT (high electron mobility transistor).
The aforementioned related techniques can be disclosed in, for example, Japanese Patent Publication No. 2792785, and Japanese Unexamined Patent Application First Publication No. 2002-118254, 2006-237235, and 2002-359201.
However, since the film stress generated by the strain added to the vicinity of the wafer surface is significantly large, and dislocation toward the wafer surface is generated from the strain, a desire to suppress the dislocation was present in the art.
Particularly, in the wafer on which a silicon epitaxial layer and a strained layer such as SiGe are formed, the epitaxial layer as a substrate surface is formed through CVD (chemical vapor deposition). Therefore, since the oxygen concentration within the epitaxial layer is very low, and extension of the generated dislocation cannot be prevented, dislocation pits may be produced during a device manufacturing process.
Accordingly, the invention is contrived in view of the above problem, and has been made to provide:
1. an epitaxial wafer having a high resistance to generation of dislocations;
2. a method of manufacturing such a silicon wafer; and
3. an epitaxial wafer that can be highly resistant to dislocation even when a high film stress is generated in the device manufacturing process after the strained layer is formed.